SEMICONDUCTOR DEVICE AND METHOD FOR DISPLACEMENT OF ALIGNMENT

PROBLEM TO BE SOLVED: To prevent failures in the formation of a metallic wiring pattern and provide a highly reliable semiconductor device by preventing thinning of an interlayer insulation film, due to the formation of marks for measuring displacements in alignment and improving the recognition acc...

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Bibliographic Details
Main Authors SHICHIJO YOICHI, MIZUKOSHI NORIO
Format Patent
LanguageEnglish
Published 29.06.2001
Edition7
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To prevent failures in the formation of a metallic wiring pattern and provide a highly reliable semiconductor device by preventing thinning of an interlayer insulation film, due to the formation of marks for measuring displacements in alignment and improving the recognition accuracy of the mark thereof. SOLUTION: This semiconductor device has a multilayer wiring structure, formed by laminating a plurality of metallic wiring layers 11a, 11b and 13a and a plurality of interlayer insulation films 10, 12 and 14. A mark 13b for measuring displacement of alignment, which is formed of a metal wiring layer on the second layer or on the upper layer, is formed in other pattern inhibited region III, and the metal wiring layer is removed in the lower side within the other pattern inhibited region III.
Bibliography:Application Number: JP19990359350