MANUFACTURING METHOD AND INSPECTION METHOD OF SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To prevent false recognition of a chip coordinate correction value due to an unstabilized electrical contact test of an inspection start chip, caused by defective pattern formation in a wafer outermost circumference. SOLUTION: In order to pass an electrical contact test for a b...

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Bibliographic Details
Main Author NAKAKUMA TETSUJI
Format Patent
LanguageEnglish
Published 08.06.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Summary:PROBLEM TO BE SOLVED: To prevent false recognition of a chip coordinate correction value due to an unstabilized electrical contact test of an inspection start chip, caused by defective pattern formation in a wafer outermost circumference. SOLUTION: In order to pass an electrical contact test for a base point chip without fail, a wafer inspection start chip is formed nearer to a wafer inside than conventionally and a chip is not formed in the outside thereof in a wafer end region for starting a wafer inspection, or it is formed nearer to a wafer inside than conventionally, only in a patterning process of a protection film on a pad after the formation of a final wiring layer.
Bibliography:Application Number: JP19990335939