METHOD FOR FORMING VERTICAL TRANSISTOR CMOS INTEGRATED CIRCUIT

• Main Authors: HERGENROTHER JOHN MICHAEL, MONROE DONALD P
• Format: Patent
• Language: English
• Published: 30.01.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To integrate a vertical transistor by providing a device with a source extending portion and a drain extending portion, where the source extending portion and the drain extending portion in a semiconductor substrate are regulated by the thickness of the doped first and third layers of a material, and by providing the second layer with a place for a gate to be formed later. SOLUTION: The active region of a device is formed by depositing at least three kinds of layers on a substrate. The first and third layers among these layers are three kinds of layers and regulate a source-extending portion which extends in a plug of a semiconductor material or a drain-extending portion. That is, in the case where the source of the device is formed under a semiconductor plug, the first layer regulates the source extending portion and the third layer regulates the drain-extending portion. In the case where the drain of the device is formed under the semiconductor plug, the first layer regulates the drain-extending portion, and the third layer regulates the source extending portion. The thickness of the second layer regulates the length of gate of the device.