SEMICONDUCTOR INTEGRATED CIRCUIT

• Main Authors: KAWASAKI TOSHIAKI, KIKUKAWA HIROHITO
• Format: Patent
• Language: English
• Published: 08.12.2000
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PROBLEM TO BE SOLVED: To prevent a latch up when a power source is supplied by delaying an operation start timing of a first power source generation circuit from an operation start timing of a second power source generation circuit with using as an input signal, an output signal of a voltage sensing circuit which detects a voltage level of an external power source when the power source is supplied and generates a signal for inverting a logic. SOLUTION: After an external power source 5 is supplied, a voltage sensing circuit 3 holds an output to 'L' until a voltage level of the external power source 5 becomes a predetermined value, and turns the output to 'H' when the voltage level becomes the predetermined value. A delay circuit 4 turns the output to 'H' a predetermined time later in response to the output 'H' of the voltage sensing circuit 3. A VDD generation circuit 1 starts operating upon receipt of the output 'H' of the delay circuit 4. A voltage level of the VDD generation circuit 1 connected to a P+ diffusion layer 9 of a PMOS transistor is prevented from being higher than a voltage level of a VPP generation circuit 2 connected to an N type substrate 11 via an N+ diffusion layer 8, and a latch up can be prevented.