METHOD FOR MANUFACTURING HIGHLY FLAT WAFER

• Main Authors: KAWAMOTO TOSHIRO, FUJINO SHUICHI, MORITA ETSURO, TAKASAKI YOSHIHIRO
• Format: Patent
• Language: English
• Published: 17.10.2000
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; DRESSING OR CONDITIONING OF ABRADING SURFACES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS; GRINDING; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; PERFORMING OPERATIONS; POLISHING; SEMICONDUCTOR DEVICES; TRANSPORTING

PROBLEM TO BE SOLVED: To provide a semiconductor wafer polishing method, capable of increasing the degree of flatness of a semiconductor wafer and preventing a reduction in the flatness degree of the semiconductor wafer immediately after the replacing of polishing cloth. SOLUTION: A polishing pressure from a first partial polishing process to a partial polishing process immediately before a finish polishing process is set larger in the outer peripheral part of a carrier plate 16 then its center part, the polishing pressure of the partial polishing process immediately before the finish polishing process is set larger in the center load of the plate 16 than its outer peripheral load, and in the finish polishing process, the center load and the outer peripheral load are set equal to each other. Thus, the degree of flatness for a silicon wafer W is increased. In addition, since the replacing of the polishing cloth 11 of a specified polishing surface plate 12 is carried out while supplying cooling water to the water jacket of a remaining polishing surface plate 12 not to be replaced, a reduction in the flatness degree of the semiconductor wafer immediately after the replacing of the polishing cloth 12 is prevented.