DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

• Main Authors: KIKUCHI ATSUSHI, HASHIMOTO TORU, SASAKI TETSUO, MINOHARA KAZUHIKO, YAMAGATA MAKOTO
• Format: Patent
• Language: English
• Published: 08.09.2000
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a design method for preparing a semiconductor integrated circuit capable of reducing the increase in a chip area and of carry out a fast operation. SOLUTION: In inter-block wiring deign 104, an inverter insertion number to be inserted to wiring between function blocks is obtained based on a wiring length between the function blocks and the allowable amount of wiring delay time and a file for indicating the correspondence of inter-block wiring to the inverter insertion number is prepared. A function logic description file is prepared in logic input 105 and a gate circuit corresponding to each of the function blocks is generated based on the function logic description file and a result obtained in timing budget design 103 in logic synthesis 106. The file obtained in the inter-block wiring design is added to input and the gate circuit corresponding to the function block provided with a polarity inverted output terminal is generated. Further, a relay inverter closest to the polarity inverted output terminal is added to the gate circuit by considering an insertion interval and output is performed as a function block file.