CLOCK PHASE CORRECTION CIRCUIT

PROBLEM TO BE SOLVED: To provide a circuit for reducing the size of a jitter by outputting an inner clock in a clock phase correction circuit, outputting a feedback clock, comparing the phases of them, outputting a detection signal, outputting a control signal, inverting an outer clock, receiving th...

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Bibliographic Details
Main Author SUNG JUN BAE
Format Patent
LanguageEnglish
Published 04.07.2000
Edition7
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a circuit for reducing the size of a jitter by outputting an inner clock in a clock phase correction circuit, outputting a feedback clock, comparing the phases of them, outputting a detection signal, outputting a control signal, inverting an outer clock, receiving the feedback clock and reducing the phase difference. SOLUTION: An outer clock is inputted to a first phase conversion part 51 and the first phase conversion part 51 selects an upper limit to which a feedback clock belongs in four upper limits. Two outputs Out 11 and Out 12 being the references of the upper limit are outputted. Outer clock Extclk and the inverse of Extclk are inputted to the first phase conversion part 51, and it outputs a signal A having the phase of 90 degrees and the signal, the inverse of A, which has the phase of 270 degrees, to a first multiplexer. A second phase conversion part 53 selects the signal A outputted by the first phase conversion part 51 and a signal Out 21 having the intermediate phase of the signal, the inverse of Extclk signal and transmits them to output Out 22.
Bibliography:Application Number: JP19990149701