INTRA-CHIP COMMUNICATION DATA COMPRESSION TECHNIQUE

PROBLEM TO BE SOLVED: To parallel perform a collation operation in compression and expansion and to perform efficient communication based on data compression between modules in a processor. SOLUTION: Data is compressed in a data transfer mode by using a memory and computing element integrated type p...

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Bibliographic Details
Main Authors KAMEYAMA MITSUTAKA, HARIYAMA SHIYOURON
Format Patent
LanguageEnglish
Published 30.06.2000
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To parallel perform a collation operation in compression and expansion and to perform efficient communication based on data compression between modules in a processor. SOLUTION: Data is compressed in a data transfer mode by using a memory and computing element integrated type parallel processor architecture for compressing and expanding data. Transmitting data is compressed in a compression module 3 of a module A1 and is transferred to a module B2. An expansion module 4 of a module B2 expands received data. In such a case, 'instantaneously decodable' algorithm, that is, such algorithm as to start to expand just after a module B receives data is used as compression algorithm. Then, it is possible to overlap expansion time 8 and transfer time 7.
Bibliography:Application Number: JP19980356516