MEMORY CELL AND METHOD FOR FORMING THE SAME

• Main Author: RUPP THOMAS S
• Format: Patent
• Language: English
• Published: 16.06.2000
• Edition: 7
• Subjects: ELECTRICITY

PROBLEM TO BE SOLVED: To reduce a conflict in spaces between separate capacitors and between each capacitor and a bit line and a word line by a method wherein the word line on a surface of a semiconductor substrate is normally buried in the interior of the semiconductor substrate. SOLUTION: Each recess part formed within a polysilicon gate conductor 15 is filled with a fill-up part 17 of a silicon compound, e.g. tungsten silicon compound, and its conductivity is increased for using it as a word line. For this reason, the fill-up part 17 of the word line is retained at a sufficiently lower side of a surface 10A. A second PAD layer and a spacer are removed, and a recess part left behind by the removal is filled with a silicon oxide 18. At that time, after the surface is coated, single crystal silicon as etch stop is used by a chemical and mechanical polishing to flatten the surface. In this manner, the word line containing the doped polysilicon 15 and silicon compound 17 is fully enclosed with a gate dielectric 14.