ALIGNMENT MARK AND SEMICONDUCTOR WAFER

PROBLEM TO BE SOLVED: To permit reliable alignment by preventing potential erroneous recognition or impossibility of recognition of a device for inspection and analysis as well as provide an alignment mark with improved alignment accuracy. SOLUTION: In an alignment mark 20 used in a semiconductor wa...

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Bibliographic Details
Main Author MATOBA KAORI
Format Patent
LanguageEnglish
Published 16.05.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
CONTROLLING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
REGULATING
SEMICONDUCTOR DEVICES
SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
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Summary:PROBLEM TO BE SOLVED: To permit reliable alignment by preventing potential erroneous recognition or impossibility of recognition of a device for inspection and analysis as well as provide an alignment mark with improved alignment accuracy. SOLUTION: In an alignment mark 20 used in a semiconductor wafer manufacturing process, only one right-angle part 26 is formed to make the pattern unique. The pattern is disposed at the same position in a chip active region 24 of each wafer. The alignment mark 20 is formed near a corner on the inward side of a scribe line 32 in the chip active region. The same material as that of members used in the manufacturing process is used for the alignment mark 20, which is made when the members are used.
Bibliography:Application Number: JP19980309032