NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND ITS TESTING METHOD
PROBLEM TO BE SOLVED: To provide the nonvolatile semiconductor storage device which can test through single measurement whether or not the thresholds of all memory cells are in a proper range after all the memory cells are set in a written or erased state. SOLUTION: This device is provided with a hi...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | English |
Published |
07.04.2000
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | PROBLEM TO BE SOLVED: To provide the nonvolatile semiconductor storage device which can test through single measurement whether or not the thresholds of all memory cells are in a proper range after all the memory cells are set in a written or erased state. SOLUTION: This device is provided with a high-order (row) address decoder 3 equipped with a word line selecting circuit 10 which activates all word lines by invalidating a decode signal HAD for selecting a word line WL in specific test mode, a 1st external terminal 8, a word line potential switching circuit 7 which controls the potentials of all activated word lines with a potential supplied to a 1st external terminal, a low-order (column) address decoder 4 equipped with a bit line selecting circuit 11 which invalidates a decode signal LAD for selecting a bit line BL and connects all the bit lines to data output lines 6, a 2nd external terminal 9, and a switching circuit SWT which connects the data output lines 6 where all the bit lines are connected to the 2nd external terminal 9. |
---|---|
AbstractList | PROBLEM TO BE SOLVED: To provide the nonvolatile semiconductor storage device which can test through single measurement whether or not the thresholds of all memory cells are in a proper range after all the memory cells are set in a written or erased state. SOLUTION: This device is provided with a high-order (row) address decoder 3 equipped with a word line selecting circuit 10 which activates all word lines by invalidating a decode signal HAD for selecting a word line WL in specific test mode, a 1st external terminal 8, a word line potential switching circuit 7 which controls the potentials of all activated word lines with a potential supplied to a 1st external terminal, a low-order (column) address decoder 4 equipped with a bit line selecting circuit 11 which invalidates a decode signal LAD for selecting a bit line BL and connects all the bit lines to data output lines 6, a 2nd external terminal 9, and a switching circuit SWT which connects the data output lines 6 where all the bit lines are connected to the 2nd external terminal 9. |
Author | KII YASUYUKI |
Author_xml | – fullname: KII YASUYUKI |
BookMark | eNrjYmDJy89L5WSw9_P3C_P3cQzx9HFVCHb19XT293MJdQ7xD1IIBhKO7q4KLq5hns6uCo5-LgqeIcEKIa7BIZ5-7gq-riEe_i48DKxpiTnFqbxQmptByc01xNlDN7UgPz61uCAxOTUvtSTeK8DIwMDA0MAASDkaE6UIAAh_LJM |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
Edition | 7 |
ExternalDocumentID | JP2000100200A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JP2000100200A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 15:27:06 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JP2000100200A3 |
Notes | Application Number: JP19980273242 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000407&DB=EPODOC&CC=JP&NR=2000100200A |
ParticipantIDs | epo_espacenet_JP2000100200A |
PublicationCentury | 2000 |
PublicationDate | 20000407 |
PublicationDateYYYYMMDD | 2000-04-07 |
PublicationDate_xml | – month: 04 year: 2000 text: 20000407 day: 07 |
PublicationDecade | 2000 |
PublicationYear | 2000 |
RelatedCompanies | SHARP CORP |
RelatedCompanies_xml | – name: SHARP CORP |
Score | 2.517807 |
Snippet | PROBLEM TO BE SOLVED: To provide the nonvolatile semiconductor storage device which can test through single measurement whether or not the thresholds of all... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING |
Title | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND ITS TESTING METHOD |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000407&DB=EPODOC&locale=&CC=JP&NR=2000100200A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3da8IwED-c-3zb3GSb2whj9K2s2ta2DyI1iVrRtNgovkm_BmNQZXbs31-a6eaTL3m4g-M4crm75HcXgJdIN1OtmdhqnJltUaDohmqnTqY6RpK-ZbphNiOJ8mXt4cwYLcxFBT52vTByTui3HI4oPCoR_l7I83r9f4lFJLZy8xq_C9Kq2-cdouyq43JPWgrpdWjgEx8rGHdGgcKmkldOG9U09wiORR5tlfgvOu-VbSnr_ZjSv4STQIjLiyuoZHkNzvHu67UanE22L941OJUQzWQjiFs33FxDl_ls7o9d7o0pCktL-ozMMPenKBSLO6CI0LmHKXIZQR4PEach99gATSgf-uQGnvuU46EqdFr-WWA5Cvb01-tQzVd5dgvITlt2amupyMJSo5UkceRYTjMuh6obmRnpd9A4IOj-ILcBF79t54aqWQ9QLT6_skcRgIv4SRruB03igqY |
link.rule.ids | 230,309,783,888,25578,76884 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8gfuCbokbFj8aYvS0OtsH2QMhYCxuObmGF8Eb2ZWJMBpEZ_327CsoTL324Sy6XS6931979CvAcqXqqNBNDjjO9zQsUVZON1MxkU0vSt0zV9GYkunxp25lqo7k-r8DHdhZG4IR-C3BE7lEJ9_dCnNer_0ssLHor1y_xOyctewPWxdK2Oi73ZEfC_S4JfOzbkm13R4FEJ4JXoo0qinUAhzzHNkqgfTLrl2Mpq92YMjiDo4CLy4tzqGR5HWr29uu1OpyMNy_edTgWLZrJmhM3bri-gB716cz3LOZ6BIWlJX2KpzbzJyjkizUkCJOZaxNkUYxcFiJGQubSIRoT5vj4Ep4GhNmOzHVa_FlgMQp29FevoJov8-wakJG2jNRQUp6FpVorSeLI7JjNuARV1zI9Um-gsUfQ7V7uI9QcNvYWnktfG3D6O4KuyUrnDqrF51d2z4NxET8II_4AltSFlg |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=NONVOLATILE+SEMICONDUCTOR+STORAGE+DEVICE+AND+ITS+TESTING+METHOD&rft.inventor=KII+YASUYUKI&rft.date=2000-04-07&rft.externalDBID=A&rft.externalDocID=JP2000100200A |