VLSI CIRCUIT AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To obtain a VLSI(very large scale integration) circuit which reduces crosstalks between metal planes and in the metal plane of the VLSI circuit, and manufacture thereof. SOLUTION: One metal plane i+1 of a VLSI chip has a wiring 1, disposed according to the design of the chip an...

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Bibliographic Details
Main Authors WENDEL DIETER, ASUM HESSEL, ERICH KLINK, PASOTAM TORIKAM PATEL, JUERGEN KEHR
Format Patent
LanguageEnglish
Published 03.03.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To obtain a VLSI(very large scale integration) circuit which reduces crosstalks between metal planes and in the metal plane of the VLSI circuit, and manufacture thereof. SOLUTION: One metal plane i+1 of a VLSI chip has a wiring 1, disposed according to the design of the chip and empty regions which have no wiring between metal lines. Channels which are not used in the empty regions are buried by voltage/ground lines 7 connected to a nearby plane (not shown). These segments are connected to voltage/ground buses 9 on a nearby plane i. The added voltage tracks and ground tracks shield wirings oriented in the same direction, to abruptly lessen the in-plane inter-line couplings or crosstalks. In addition, the inter-line coupling between vertical planes reduces approximately down to zero.
Bibliography:Application Number: JP19990108585