METHOD OF FORMING CAPACITORS IN INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a method which has compatibility with the existing CMOS components manufacturing process in manufacturing a capacitor, having little possibility of causing the dielectric breakdown. SOLUTION: A first metal layer is deposited and etched with leaving a region 12, corre...

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Main Authors BANVILLET HENRI, GUELEN JOS, OBERLIN JEAN-CLAUDE, MOURIER JOCELYNE, LUNARDI GENEVIEVE, MADDALON CATHERINE, GRIS YVON, TROILLARD GERMAINE
Format Patent
LanguageEnglish
Published 18.02.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a method which has compatibility with the existing CMOS components manufacturing process in manufacturing a capacitor, having little possibility of causing the dielectric breakdown. SOLUTION: A first metal layer is deposited and etched with leaving a region 12, corresponding to a capacitor plate and contact region 13 on the first metal layer, an input layer 15 is deposited between metallization layers, a first opening is formed into an upper part of the capacitor plate 12, a thin insulation layer 17 is deposited, a second opening 20 is formed into an upper part of the contact region, a second metal layer 24 is deposited for completely filling the opening 20, a physical-chemical etching is applied to suppress the outside region of the second metal layer, and a third metal layer is deposited to cause to be left at positions 31, 32 on the third metal layer above the contact region and capacitor region.
Bibliography:Application Number: JP19990198895