VERIFICATION DEVICE FOR LSI DESIGN

PROBLEM TO BE SOLVED: To provide a verification device for LSI design capable of detecting wiring for which an allowable current value becomes a violation in a minimum wiring width from a circuit simulated result and preventing an allowable current capacity error on layout pattern design. SOLUTION:...

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Bibliographic Details
Main Author HISADA TOSHIMASA
Format Patent
LanguageEnglish
Published 02.02.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a verification device for LSI design capable of detecting wiring for which an allowable current value becomes a violation in a minimum wiring width from a circuit simulated result and preventing an allowable current capacity error on layout pattern design. SOLUTION: The verification device for the LSI design for verifying a current capacity value is provided with a means 7 for calculating the allowable current value of the minimum wiring width and detecting a device terminal exceeding the allowable current value and the means 8 for comparing and verifying a circuit diagram and the connection information of a layout pattern and emphasis-displaying the wiring on a layout diagram connected to the terminal detected by the means 7 for detecting the device terminal exceeding the allowable current value.
Bibliography:Application Number: JP19980205267