INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To provide a bus system for an information processor capable of maximizing the application efficiency of three kinds of buses, i.e., a system bus, a memory bus and a processor bus. SOLUTION: A processor bus 111 connected to plural processors 101, a memory bus 112 connected to a...

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Bibliographic Details
Main Authors MOCHIDA TETSUYA, KAWAGUCHI HITOSHI, KOBAYASHI ICHIJI, KIMURA KOICHI, OKAZAWA KOICHI, YUNO KAZUHARU
Format Patent
LanguageEnglish
Published 28.01.2000
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide a bus system for an information processor capable of maximizing the application efficiency of three kinds of buses, i.e., a system bus, a memory bus and a processor bus. SOLUTION: A processor bus 111 connected to plural processors 101, a memory bus 112 connected to a main memory 104 and a system bus 113 connected to plural I/O devices 105 are connected to a three-line connection control means 103. The means 103 connected to respective address buses and control buses of the processor bus 111, the memory bus 112 and the system bus 113 has a bus/memory connection controller 401 for mutually transferring address and control signals and generating a data bus control signal. The means 103 connected also to respective data buses of the processor bus 111, the memory bus 112 and the system bus 113 has a data bus switch 402 for mutually transferring data on these data buses in accordance with a data bus control signal 420.
Bibliography:Application Number: JP19990008640