Stack Patterning

A method of forming a stack of layers 4 defining electrical circuitry and comprising a plurality of inorganic conductor levels 6a, 6b, 6c, 14, 20, wherein the conductor levels are formed in multiple stages. The conductor 14 may provide a mask for creating via-holes through the underlying organic lay...

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Bibliographic Details
Main Authors Josephine Socratous, Neil Murton, Herve Vandekerckhove
Format Patent
LanguageEnglish
Published 03.02.2021
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method of forming a stack of layers 4 defining electrical circuitry and comprising a plurality of inorganic conductor levels 6a, 6b, 6c, 14, 20, wherein the conductor levels are formed in multiple stages. The conductor 14 may provide a mask for creating via-holes through the underlying organic layer 12 at which the conductor 20 is to contact another conductor 6a at a lower conductor level. The conductor 20 may be formed by depositing conductor material in the region of the via holes. Depositing the conductor material may comprise depositing a sub-stack of conductor layers. The underlaying organic layer 12 may comprise a non-cross-linked polymer layer, or an organic polymer dielectric layer, and may be patterned using a solution of organic photoresist material. The conductors 14, 20 may comprise a gate conductor pattern for a transistor array. The technique may be used to produce an OLCD or OTFT device.
Bibliography:Application Number: GB20190010884