Interconnection network for integrated circuit
An integrated circuit 200 consists of nodes connected by an interconnect. A transmission path 202 in the interconnect transfers data blocks from an upstream location 203 to a downstream location 205. A digest of the data, such as a cyclic redundancy check (CRC) code is generated 204 from the block a...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
18.12.2019
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Subjects | |
Online Access | Get full text |
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Summary: | An integrated circuit 200 consists of nodes connected by an interconnect. A transmission path 202 in the interconnect transfers data blocks from an upstream location 203 to a downstream location 205. A digest of the data, such as a cyclic redundancy check (CRC) code is generated 204 from the block at the upstream location. A further digest is generated 206 at the downstream location. The two digests are compared 216 to determine if the data block was transmitted successfully. The upstream digests may be stored in a buffer 208. If the interconnect retains the order of the data blocks transmitted between the locations, the buffer may store multiple digests in order. Alternatively, if there are multiple transmission paths between the locations, the buffer may associate data block identifiers with the digests. In this case, the ordering of the digests also may be checked to detect an error. |
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Bibliography: | Application Number: GB20180009602 |