An apparatus and method of executing thread groups

An apparatus comprises scheduling circuitry 10 to select for execution a first threadgroup, and thread processing circuitry 30 to execute active threads of the first thread group in dependence on a common program counter 20 shared between the active threads (e.g. SIMT). In response to an exit event...

Full description

Saved in:
Bibliographic Details
Main Authors Eugenia Cordero-Crespo, Isidoros Sideris, Amir Kleen
Format Patent
LanguageEnglish
Published 13.03.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:An apparatus comprises scheduling circuitry 10 to select for execution a first threadgroup, and thread processing circuitry 30 to execute active threads of the first thread group in dependence on a common program counter 20 shared between the active threads (e.g. SIMT). In response to an exit event 60 (e.g. branch instruction) occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present 40, which triggers program counter checking circuitry 50 to perform a program counter check operation to update the common program counter 70 and an active thread indication for the first thread group. The thread processing circuitry is provided with register storage (e.g. 39) in which program counter information for each thread of the first thread group can be stored (80 in Figure 2), and the program counter checking circuitry has access to this. The scheduling circuitry is arranged to select for execution a different thread group whilst awaiting performance of the program counter check operation (e.g. sorting to find a minimum value) for the first thread group (* in Figure 6). This facilitates efficiently handling thread divergence and re-convergence.
Bibliography:Application Number: GB20170016642