Power efficient processor architecture

• Main Authors: Ravishankar Iyer, Srihari Makineni, Rameshkumar G Illikkal, Jaideep Moses, Andrew J Herdrich, Sadagopan Srinivasan
• Format: Patent
• Language: English
• Published: 12.10.2016
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A processor 100, comprises a first 110 and second 120 plurality of cores; wherein the second plurality of cores has a lower power consumption when in operation than the first; an interconnect to couple the first and second cores; and a shared cache memory coupled to at least the first cores; wherein, based at least in part on a performance requirement, an execution state of the core of the second cores to be transferred to a core of the first plurality of cores to enable the core of the first cores to execute the operation. The processor may also comprise logic such that the second of cores and not the first are awoken in response to an interrupt when the pluralities of cores are in a low power state. The logic may also awaken the first cores in response to the interrupt when an entry of a table indicates the second cores incurred an undefined fault in response to a previous interrupt of the same type.