Wafer metallization of high power semiconductor devices

• Main Authors: Maolong Ke, Ian Francis Deviny
• Format: Patent
• Language: English
• Published: 09.10.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A power semiconductor device for high current density applications, i.e. an insulated gate bipolar transistor (IGBT) or MOSFET, comprising: a plurality of semiconductor regions (201, 203, 204, figure 2) formed on top of one another and a contact layer (207) formed above a first surface of one of the semiconductor regions. The contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region (209) formed in direct contact of said first surface of said one of the semiconductor regions. The device further comprises a first metal layer (230, 235) formed at least partly on the second portion of the contact layer; and a second metal layer 240 formed at least partly on the first metal layer. A gap or void present between the second metal layer and contact layer reduces pressure during fabrication. This structure is suitable for the pressure pack, double sided silver sintering or double sided soldering packaging process.