Processors with support for compact branch instructions & methods

Aspects relate to microprocessors, methods of their operation, and compilers therefor, that provide branch instructions with and without a delay slot. Branch instructions without a delay slot may have a forbidden slot. A processor, when decoding and executing a branch instruction without a delay slo...

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Bibliographic Details
Main Author Ranganathan Sudhakar
Format Patent
LanguageEnglish
Published 03.08.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Aspects relate to microprocessors, methods of their operation, and compilers therefor, that provide branch instructions with and without a delay slot. Branch instructions without a delay slot may have a forbidden slot. A processor, when decoding and executing a branch instruction without a delay slot, at a program counter location, executes an instruction in a subsequent program counter location (a "forbidden slot", in some implementations) only if the branch is not taken. A pre-determined set of instruction types may be identified, and if an instruction location in the forbidden slot is from the pre-determined set of instruction types, implementations may throw an exception without executing the instruction, or may execute the instruction and throw an exception after execution. Such exceptions may be dependent or independent on an outcome of executing the instruction itself.
Bibliography:Application Number: GB20150020669