Ultra low power transistor for 40nm processes

Methods of fabricating ultra-low power transistors with a lightly doped drain (LDD) region 206 and pocket (or halo) implant regions 208, the method involves optimising the LDD and pocket doping levels for hot carrier injection (HCI) failure time and off (i.e. leakage) current and using the lowest do...

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Bibliographic Details
Main Authors DAVID VIGAR, DAVE VERITY, RAINER HERBERHOLZ
Format Patent
LanguageEnglish
Published 30.09.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods of fabricating ultra-low power transistors with a lightly doped drain (LDD) region 206 and pocket (or halo) implant regions 208, the method involves optimising the LDD and pocket doping levels for hot carrier injection (HCI) failure time and off (i.e. leakage) current and using the lowest doping possible while maintaining acceptable failure rates. By optimizing a MOSFET for low junction off current rather than speed/on current, a MOSFET can be produced which still meets the HCI reliability specification but has significantly reduced power consumption when off. This is in contrast to standard MOSFETs which are optimized for speed/on current and have an LDD dose which, if increased further, would cause the device to no longer pass the HCI reliability specification.
Bibliography:Application Number: GB20140005181