Enhanced data retention mode for dynamic memories

A memory device includes one or more memory cells, each of the memory cells having corresponding bit and word lines connected thereto for individually accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The m...

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Bibliographic Details
Main Authors MICHAEL SPERLING, WILLIAM ROBERT REOHR, ROBERT KEVIN MONTOYE
Format Patent
LanguageEnglish
Published 27.08.2014
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes one or more memory cells, each of the memory cells having corresponding bit and word lines connected thereto for individually accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative, via the bit and word line circuits, and the bit and word lines, to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal, in a data retention mode, for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
Bibliography:Application Number: GB20140010074