Flattened substrate surface for substrate bonding

Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for...

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Bibliographic Details
Main Authors DALE W MARTIN, EDMUND J SPROGIS, EDWARD C COONEY, JAMES S DUNN, CHARLES F MUSANTE, LEATHEN SHI, CORNELIA K TSANG, BETH-ANN RAINEY
Format Patent
LanguageEnglish
Published 09.07.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
Bibliography:Application Number: GB20140008711