Connecting an external network coprocessor to a network processor packet parser

Optimizing the number of lanes of a network processor when implementing a request/response traffic between the parser of network processor Ethernet ports and an external coprocessor comprises at reception of a 64 byte Ethernet packet in the Ethernet port, and during parsing time, the parser sending...

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Bibliographic Details
Main Authors CLAUDE BASSO, CHIH-JEN CHANG, NATARAJAN VAIDHYANATHAN, COLIN VERRILLI, DAMON PHILIPPE, JEAN L CALVIGNAC, FABRICE J VERPLANKEN
Format Patent
LanguageEnglish
Published 18.12.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:Optimizing the number of lanes of a network processor when implementing a request/response traffic between the parser of network processor Ethernet ports and an external coprocessor comprises at reception of a 64 byte Ethernet packet in the Ethernet port, and during parsing time, the parser sending a request 16 byte word to the coprocessor on the 3.125 additional (bidirectional) lane and receiving a 16 byte word in response on the 3.125 additional (bidirectional) lane. Coprocessor access 16 byte word traffic and one (bidirectional) traffic with one unit in the network processor may be multiplexed statically, one or the other traffic being set when the network processor is initialized. Dynamic multiplexing of the coprocessor access 16 byte word traffic in one Ethernet port and the coprocessor access 16 byte word traffic in one other Ethernet port is performed, the dynamic multiplexing being arbitrated with a round robin algorithm.
Bibliography:Application Number: GB20130012922