Solving control bits of butterfly networks in Turbo decoders

Control bits for switches of a butterfly network are directly solved (314) iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus inde...

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Bibliographic Details
Main Author ESKO JUHANI NIEMINEN
Format Patent
LanguageEnglish
Published 26.12.2012
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
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Summary:Control bits for switches of a butterfly network are directly solved (314) iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network arc generated. A linear order bus index and. a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear order and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver.
Bibliography:Application Number: GB20120011610