A MEMORY CONTROLLER TO SUPPORT DATA SWIZZLING AND DE-SWIZZLING

A memory controller (120) determines a swizzling pattern between the memory controller and memory devices (140) to allow error correction mechanisms such as error correction codes (ECC) to operate effectively. The memory controller uses a training process (fig. 3) to generate a swizzling map based o...

Full description

Saved in:
Bibliographic Details
Main Authors JOSEPH H SALMON, KULJIT S BAINS
Format Patent
LanguageEnglish
Published 29.06.2011
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A memory controller (120) determines a swizzling pattern between the memory controller and memory devices (140) to allow error correction mechanisms such as error correction codes (ECC) to operate effectively. The memory controller uses a training process (fig. 3) to generate a swizzling map based on the determined swizzling pattern. To generate the swizzling map the memory controller, for at least N combinations (i.e. patterns) of N bits, writes (300) a bit combination to a multi-purpose register in a memory device over a non-szizzled bus and reads (310) the bit combination from the register over a swizzled bus. For writes, the memory controller performs 400 error correcting code operations on data to be written and then rearranges 420 data bits using the swizzling map before writing 430 the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data (510) using the swizzling map before performing error correction operations (520). The training pattern may be a walking "0" or walking "1" pattern.
Bibliography:Application Number: GB20100021586