Generating a second clock signal from a first clock signal based upon a delayed control signal

• Main Author: TSUNEKI SASAKI
• Format: Patent
• Language: English
• Published: 20.05.2009
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A dock signal generation circuit 700 receives a first clock signal CLK and a control signal (ctl_en or pre_wr_RAMCLK) based on an address ADDR are inputted. A second clock signal RAMCLK based on said first clock signal is generated after a delay of predetermined time from said input of the control signal. The described embodiment refers to a control circuit 10 for connection between a memory controller 100 and memory 200 which comprises the clock generation circuit, a control signal generation circuit 600 and a latency control circuit 500. The latency controller has a latency register 520 into which is stored a latency value and a latency counter 510 which decrements the value to zero whereupon the latency controller outputs a signal enabling the clock generator. The latency value can be programmed by the memory controller based upon the type of operation being performed such that the delay in generating the clock signal can be greater for write operations than read operations. This is to secure a setup time for write operations without unduly delaying read operations and prevent setup violations.