Memory device having trapezoidal bitlines and method of fabricating same

A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrical...

Full description

Saved in:
Bibliographic Details
Main Authors MARK T RAMSBEY, MARK W RANDOLPH
Format Patent
LanguageEnglish
Published 16.07.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
Bibliography:Application Number: GB20070013510