Stall control and re-synchronisation in a multi-pipeline processor

In a multi-pipeline (14 and 16, fig. 1) processor having multiple stages in each pipeline 42, 52, 62, 72, a stall generated in one stage will immediately hold that, and all preceding stages, in that pipeline, and generates a global stall signal that operates one or more clock cycles later to hold th...

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Bibliographic Details
Main Authors NIGEL PETER TOPHAM, KAR-LIK KASIM WONG
Format Patent
LanguageEnglish
Published 15.05.2002
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:In a multi-pipeline (14 and 16, fig. 1) processor having multiple stages in each pipeline 42, 52, 62, 72, a stall generated in one stage will immediately hold that, and all preceding stages, in that pipeline, and generates a global stall signal that operates one or more clock cycles later to hold the next stage, and all preceding stages, in the other pipelines. When the stall is released all stages of that pipeline are immediately released, and the other pipelines are released one, or more, clock cycles later following release of the global signal, so ensuring that data within the pipelines is once more synchronous. The method can also be applied to multiple pipelines arranged into multiple clusters within a processor (fig. 4), and to stalls occurring at different stages in different clusters of the pipeline.
Bibliography:Application Number: GB20010024552