Fabricating hetro-junction bipolar transistors
Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is reduced by using a metallic silicide as the base (25), comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region (21); growing a collect...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
26.06.1996
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is reduced by using a metallic silicide as the base (25), comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region (21); growing a collector epitaxial layer (22) on the buried collector region and forming a field oxide layer (23); selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer (25) and a first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film (26) thereon to form a base electrode thin film; forming a capping oxide layer (27), forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask, removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes. |
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Bibliography: | Application Number: GB19940025590 |