Digital data rounding

A data rounding circuit (10) for rounding ten-bit digital data (a) to eight bits includes a bit pattern generator (22) for generating at least four bit patterns PTN0 to PTN3 each comprising at least two single-bit samples, wherein one of the fixed bit patterns PTN0 to PTN3 is selected in accordance...

Full description

Saved in:
Bibliographic Details
Main Author TETSURO NAKATA
Format Patent
LanguageEnglish
Published 23.02.1994
Edition5
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
Online AccessGet full text

Cover

More Information
Summary:A data rounding circuit (10) for rounding ten-bit digital data (a) to eight bits includes a bit pattern generator (22) for generating at least four bit patterns PTN0 to PTN3 each comprising at least two single-bit samples, wherein one of the fixed bit patterns PTN0 to PTN3 is selected in accordance with the value of the low-order two bits (c) of the ten-bit digital data (a) to be rounded and added to the high-order eight bits (b) thereof to produce rounded eight-bit data (e). The circuit can be used to round 10-bit digital video signals to 8-bit data where the use of fixed bit patterns improves the overall picture quality. In addition, by changing the ordering of the single-bit samples in a fixed bit pattern, the adverse generation of an inherent vertical bit pattern can be prevented. A method of recovering the truncated bits to restore the original ten-bit data is also disclosed.
Bibliography:Application Number: GB19930017126