METHOD OF PLANARISING A SEMICONDUCTOR DEVICE

The method comprises the steps of: forming and patterning a first metal layer 11, which is not anodized, to a predetermined thickness d1 on a substrate 10, forming a second metal layer 12 which is anodized, forming a mask corresponding to the lateral dimensions of the first patterned metal layer on...

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Bibliographic Details
Main Authors INSIK JANG, NAMDEOG KIM, JEONGHA SOHN, SANGSOO KIM, HYUNGTAEK KIM, BYUNGSEONG BAE
Format Patent
LanguageEnglish
Published 04.11.1992
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The method comprises the steps of: forming and patterning a first metal layer 11, which is not anodized, to a predetermined thickness d1 on a substrate 10, forming a second metal layer 12 which is anodized, forming a mask corresponding to the lateral dimensions of the first patterned metal layer on the second metal layer and forming a planar surface by anodic oxidation of the second metal layer in order that regions 15 form a planar insulator. Part of the second layer 12 below the mask may also be anodised in forming the planar insulator. The electrode formed by the layers may be the gate of a thin film F.E.T.
Bibliography:Application Number: GB19910027095