VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM

A circuit is described for providing internal voltage margining for a flash EPROM to verify erasing and programming. Matched transistors are used to develop the internal margined voltage so as to provide a potential which is substantially independent of process variations. Different potentials are u...

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Bibliographic Details
Main Author OWEN W JUNGROTH
Format Patent
LanguageEnglish
Published 31.08.1989
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A circuit is described for providing internal voltage margining for a flash EPROM to verify erasing and programming. Matched transistors are used to develop the internal margined voltage so as to provide a potential which is substantially independent of process variations. Different potentials are used to verify programming and erasing.
Bibliography:Application Number: GB19880019691