IMPROVEMENTS IN AND RELATING TO MONOLITHIC DATA STORAGE MATRICES
1299113 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 4 March 1970 [11 March 1969] 10254/70 Heading H1K [Also in Divisions G4 and H3] In a matrix of bi-stable cells each (Fig. 1, not shown) has a pair of diodes (D1, D2) connecting its collector loads (R1, R0) to a respective pair of bi...
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Main Author | |
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Format | Patent |
Language | English |
Published |
06.12.1972
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Subjects | |
Online Access | Get full text |
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Summary: | 1299113 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 4 March 1970 [11 March 1969] 10254/70 Heading H1K [Also in Divisions G4 and H3] In a matrix of bi-stable cells each (Fig. 1, not shown) has a pair of diodes (D1, D2) connecting its collector loads (R1, R0) to a respective pair of bit lines (B1, B0) which have resistors (R0) lower than R1, R2 acting as loads for the bistable when it is addressed. In integrated form, Figs. 3, 3A, each transistor has an N epitaxial layer forming the collector, an N+ emitter region contacted by the W line, and a P base region contacted by a connector B and extended to contact the V1 line, the resistor R1 or R2 being formed in this extended P region as a pinch resistor by a covering N+ diffusion. This diffusion also forms a connection to the collector region and is connected by a metal connector to the opposite base B. The diodes D1, D2 are formed in the epitaxial layer N. P + isolation zones are provided, and the layout is said to require a reduced number of isolation zones to carry all the components. The resistors R1, R2 may be formed alternatively as further, complementary, transistors. |
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Bibliography: | Application Number: GB19700010254 |