IMPROVEMENTS IN OR RELATING TO TELECOMMUNICATIONS SYSTEMS

1,217,672. Multiplex pulse code signalling. GENERAL ELECTRIC, and ENGLISH ELECTRIC COMPANIES Ltd. 2 Feb., 1968 [1 Dec., 1966], No. 53879/66. Heading H4L. In a P.C.M. communication system for twoway signalling, each station has a local oscillator which controls the repetition frequency of the transmi...

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Bibliographic Details
Main Authors DONALD FRANCIS BOWMAN, ALLEN ALLISTER CLAXTON
Format Patent
LanguageEnglish
Published 31.12.1970
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Summary:1,217,672. Multiplex pulse code signalling. GENERAL ELECTRIC, and ENGLISH ELECTRIC COMPANIES Ltd. 2 Feb., 1968 [1 Dec., 1966], No. 53879/66. Heading H4L. In a P.C.M. communication system for twoway signalling, each station has a local oscillator which controls the repetition frequency of the transmitted pulse signal and a phase-locking control system for the oscillator which operates in dependence upon a comparison of a signal derived from the received pulse signal with a signal derived from the oscillator the two signals having nominally the same frequency which is a submultiple of the frequency of the oscillator. Fig. 1 shows a system, not incorporating the invention, in which two exchanges 1, 2 are linked 3, 4 for two-way P.C.M. speech signals, the transit times of the paths 3 and 4 being shown as delays 13, 14. Each exchange has a bit-frequency oscillator 5 from which timing signals for coding, decoding, multiplexing and demultiplexing are derived at 6. The incoming bit frequency is derived at 11 and compared with the output of oscillator 5 in a phase comparator 12 whose -output controls the frequency of oscillator 5. The invention provides a modification, Fig. 2, in which the comparison at 12 is made at the frame rate derived at 19 from the incoming signal and the frame rate also is derived at 21 from the incoming signal and supplied to a further phase comparator 20 where it is compared with the output of oscillator 5 divided at 17 to the frame rate. The output of the comparator 20 adjusts a variable delay line 18 which alternatively may be placed in the outgoing line. In a further modification Fig. 3 (not shown) the incoming signals are supplied to a buffer store from which they are read subsequently, and variable delay line is replaced by a monstable circuit which is voltage-controlled to vary the duration of its output pulses to provide a variable time delay.
Bibliography:Application Number: GB19660053879