PROCEDE ET DISPOSITIF DE CONTROLE DES RACCORDEMENTS D'UN SEMI-CONDUCTEUR

The testing method has offset potential levels applied to each two adjacent semiconductor component terminals (2a,2b), with monitoring of the component current during application of the latter potential levels. An Independent claim for a testing device for a semiconductor component is also included.

Saved in:
Bibliographic Details
Main Authors AUE AXEL, GAGEA LEONARD
Format Patent
LanguageFrench
Published 29.07.2005
Edition7
Subjects
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PRINTED CIRCUITS
TESTING
Online AccessGet full text

Cover

More Information
Summary:The testing method has offset potential levels applied to each two adjacent semiconductor component terminals (2a,2b), with monitoring of the component current during application of the latter potential levels. An Independent claim for a testing device for a semiconductor component is also included.
Bibliography:Application Number: FR20000016884