TRANSISTOR MOS A FAIBLE RESISTANCE DE DRAIN

A novel MOS transistor has an L-shaped spacer (71, 72) on each side of its gate, with the vertical limb of the L resting against the gate, and has doped source and drain regions including a first doped zone (73, 74) below the horizontal limb of each L, a second more heavily doped zone (75, 76) beyon...

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Bibliographic Details
Main Authors SCHWARTZMANN THIERRY, FRANCOU JEAN MARC, MARTY MICHEL
Format Patent
LanguageFrench
Published 02.07.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A novel MOS transistor has an L-shaped spacer (71, 72) on each side of its gate, with the vertical limb of the L resting against the gate, and has doped source and drain regions including a first doped zone (73, 74) below the horizontal limb of each L, a second more heavily doped zone (75, 76) beyond each L and preferably a third more lightly doped zone (31, 32) below the vertical limb of each L. Also claimed is production of a MOS transistor with stepped drain and source doping levels by forming an L-shaped silicon nitride spacer (71, 72) on each side of a gate region (5) and carrying out implantation only partially masked by the horizontal limb of each L.
Bibliography:Application Number: FR19970002458