Circuit de redondance de mémoire

The circuit includes a content addressable memory (CAM) storing addresses of faulty elements in a principal memory (MP). In use, incoming addresses (ADD) are compared with defective addresses stored in the content addressable memory (CAM) and where identical they are readdressed to a redundant memor...

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Bibliographic Details
Main Author DEVIN JEAN
Format Patent
LanguageFrench
Published 27.09.1996
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The circuit includes a content addressable memory (CAM) storing addresses of faulty elements in a principal memory (MP). In use, incoming addresses (ADD) are compared with defective addresses stored in the content addressable memory (CAM) and where identical they are readdressed to a redundant memory (MR). Where the principal memory (MP) has no defects time may be saved by using an inhibiting circuit (IN). If the inhibiting circuit (IN) emits a validating signal (VAL) operation is normal but an inhibiting signal (INH) prevents comparison of addresses and all addresses proceed to the principal memory (MP).
Bibliography:Application Number: FR19940002282