PROCESSUS DE FABRICATION D'ELEMENTS RESISTANTS POUR CIRCUITS INTEGRES

L'INVENTION CONCERNE UN PROCESSUS DE FABRICATION D'ELEMENTS RESISTANTS POUR CIRCUITS INTEGRES. ELLE EST CARACTERISEE PAR LE FAIT QU'IL COMPORTE LA FORMATION D'UN REVETEMENT ISOLANT COMPORTANT AU MOINS UNE ZONE ABAISSEE SE RACCORDANT AU RESTE DU REVETEMENT PAR UN EPAULEMENT FORMAN...

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Main Authors DANIELE VINCENZO, VINCENZO DANIELE, GIUSEPPE CORDA, ANDREA RAVAGLIA ET GIUSEPPE FERLA, RAVAGLIA ANDREA, FERLA GIUSEPPE, CORDA GIUSEPPE
Format Patent
LanguageFrench
Published 23.11.1979
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Summary:L'INVENTION CONCERNE UN PROCESSUS DE FABRICATION D'ELEMENTS RESISTANTS POUR CIRCUITS INTEGRES. ELLE EST CARACTERISEE PAR LE FAIT QU'IL COMPORTE LA FORMATION D'UN REVETEMENT ISOLANT COMPORTANT AU MOINS UNE ZONE ABAISSEE SE RACCORDANT AU RESTE DU REVETEMENT PAR UN EPAULEMENT FORMANT UN CANAL; L'APPLICATION D'UNE COUCHE D'UN MATERIAU NON ISOLANT ET L'ENLEVEMENT D'AU MOINS UNE REGION DE CETTE COUCHE SANS ELIMINATION DU MATERIAU APPLIQUE SUR LES PAROIS DU CANAL. L'INVENTION S'APPLIQUE EN ELECTRONIQUE. Filiform elements of predetermined resistivity, e.g. selectively destructible leads of an electrically programmable read-only memory, are formed on a semiconductor substrate such as a silicon body by first depositing thereon a layer of dielectric material such as SiO2 and topping that layer with a conductive or nonconductive coating which is resistant to a chemical such as hydrofluoric acid capable of attacking the dielectric layer. Next, the top coating is partly destroyed by photolithographic treatment to leave at least one substantially rectangular patch. Thereafter, the dielectric layer is isotropically attacked by the aforementioned chemical with resulting reduction to about half its original thickness and concurrent lateral erosion of a patch-supporting pedestal of that layer whereby channels of generally semicylindrical concavity are formed around the periphery of this pedestal. The patch, if composed of conductive or semiconductive material, is then clad in an insulating envelope whereupon the dielectric layer and the patch are covered with a deposit of the desired electrical conductivity which could consist of doped polycrystalline silicon or of metal. Finally, this deposit is removed by chemical or ionic etching except in the channels of the pedestal and along a pair of parallel strips adjoining opposite pedestal sides whereby these strips remain electrically interconnected by filiform inserts left in the undercuts of the other two sides.
Bibliography:Application Number: FR19790010763