CIRCUIT LOGIQUE INTEGRE A DENSITE ELEVEE

• Main Author: VENKAPPA L. GANI ET FRANK A. MONTEGARI
• Format: Patent
• Language: French
• Published: 20.07.1979
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES

CIRCUIT LOGIQUE INTEGRE A DENSITE ELEVEE.CHAQUE CELLULE DE CIRCUIT LOGIQUE COMPREND UN TRANSISTOR T10, T20, T30 ET PLUSIEURS DIODES A BARRIERE DE SCHOTTKY D11 A D15, D21 A D25, D31 A D35, PLUSIEURS CELLULES ETANT INTERCONNECTEES POUR REALISER LA FONCTION LOGIQUE DESIREE. LA METALLURGIE D'INTERCONNEXION POUVANT AVOIR UNE RESISTANCE ELEVEE R, L'EFFET DE CELLE-CI EST SUPPRIME EN COMMANDANT LA BASE DU TRANSISTOR RECEPTEUR T30 A TRAVERS UNE RESISTANCE DE COMMANDE DE BASE R15 DANS LA CELLULE EMETTRICE. LA CONNEXION ENTRE RESISTANCE ET DIODE DANS LES AUTRES CELLULES EST INTERROMPUE, PAR EXEMPLE ENTRE D25 ET R25. DONNE UNE PLUS GRANDE INSENSIBILITE A LA LONGUEUR DE LA METALLURGIE.PEUT ETRE UTILISE DANS TOUS LES CIRCUITS LOGIQUES A DIODES A BARRIERE DE SCHOTTKY. The disclosed logic circuit includes one transistor and a plurality of Schottky barrier diodes in each logic circuit "cell," a plurality of such cells being interconnected to perform desired logic functions. Cell interconnections are made by interconnecting metallurgy which can have a relatively high resistance with relatively long interconnecting paths between a sending circuit cell and a receiving circuit cell. The undesirable effects of this metallurgy resistance are overcome by driving the base of the receiving transistor through a base drive resistor in the sending cell.