Suoralla digitaalisella syntetisaattorilla ohjattu PLL-taajuussyntetisaattori, johon kuuluu tyhjennys PLL

• Main Author: GILMORE, ROBERT P
• Format: Patent
• Language: Finnish; Swedish
• Published: 14.11.1997
• Edition: 6
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time. Yet another embodiment uses a switching apparatus to bypass the "clean-up" PLL while it is settling on a new frequency. Once the "clean-up" PLL settles on the new frequency the switches are set to couple the "clean-up" PLL back into the synthesizer apparatus.