Digitaalisen signaalin lukituspiiri

A digital signal clamp circuit is realized using an adder (28) and an up/down counter (18). The digital signal is coupled to one input of the adder (28) and the counter output is coupled to a second input of the adder. The up/down counter (18) is enabled to count only during signal intervals exhibit...

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Bibliographic Details
Main Author FLING,RUSSELL THOMAS
Format Patent
LanguageFinnish
Swedish
Published 10.07.1996
Edition6
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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Summary:A digital signal clamp circuit is realized using an adder (28) and an up/down counter (18). The digital signal is coupled to one input of the adder (28) and the counter output is coupled to a second input of the adder. The up/down counter (18) is enabled to count only during signal intervals exhibiting the desired clamping level. The counter is controlled to count up or down depending on the polarity of the signal provided by the adder. The count value in the counter is continuously applied to the adder to provide clamping. Using a truncated count value from the counter enhances clamping performance.
Bibliography:Application Number: FI19900001552