TRANSISTORES DE EFECTO DE CAMPO DE UNION VERTICAL

• Main Authors: MEYERSON, BERNARD S, ISMAIL, KAHLID EZZELDIN
• Format: Patent
• Language: Spanish
• Published: 01.02.2008
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

SE DESCRIBE UN TRANSISTOR DE EFECTO DE CAMPO DE UNION (10) Y UN METODO PARA PRODUCIRLO, QUE INCORPORAN CAPAS SEMICONDUCTORAS HORIZONTALES (14, 16, 18, 30, 34, 38) EN UNA ABERTURA (24) PARA FORMAR UN CANAL (36), Y UNA CAPA SEMICONDUCTORA, A TRAVES DE LA CUAL SE PRACTICA LA ABERTURA, QUE FORMA UN ELECTRODO DE PUERTA (19) QUE RODEA EL CANAL. LAS CAPAS SEMICONDUCTORAS HORIZONTALES PUEDEN SER UNA ALEACION SIGE CON GRADIENTE DE COMPOSICION CERCA DEL EMISOR Y DEL COLECTOR. LA INVENCION SOLUCIONA EL PROBLEMA DE LA FORMACION DE JFETS DE BAJA RESISTENCIA, Y PROPORCIONA UNA LONGITUD DE PUERTA FACILMENTE ESCALABLE A DIMENSIONES INFERIORES AL MICRON PARA CIRCUITOS DE RF, MICROONDAS, MILIMETRICOS Y LOGICOS, SIN EFECTOS DE ACORTAMIENTO DEL CANAL. A junction field effect transistor comprises a lightly doped second semiconductor layer (16) over a first semiconductor layer of the same dopant type (14), a third semiconductor layer of opposite type (18) having an opening (24) and a dielectric layer (20) having an opening above the first opening. A fourth semiconductor layer of first type Si1-x Gex, where x increases with thickness is formed in the opening (30) and a fifth layer of first type Si1-y Gey, where y is constant with thickness, is also formed in the opening of the third layer (34). A sixth such layer of Si1-zGez, where z decreases with thickness, (38) is formed in the opening of the dielectric layer. Also claimed is a method of forming the JFET above by sequentially forming the layers and openings as above.