SELF-ALIGNED WIDE BACKSIDE POWER RAIL CONTACTS TO MULTIPLE TRANSISTOR SOURCES

• Main Authors: PARIKH, Suketu Arun, YANG, Yen-Chu, BAZIZI, El Mehdi, BERKENS, Martinus Maria, PAL, Ashish, INGLE, Nitin K, PRANATHARTHIHARAN, Balasubramanian, SEE, Guan Huei, YEOH, Andrew, DESHPANDE, Sameer A, SUNDARRAJAN, Arvind
• Format: Patent
• Language: English; French; German
• Published: 10.07.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.