RESISTIVE MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE, METHODS OF MANUFACTURING AND OPERATING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE RESISTIVE MEMORY DEVICE
Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure...
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Main Authors | , , , , , , , , , |
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Format | Patent |
Language | English French German |
Published |
03.07.2024
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Subjects | |
Online Access | Get full text |
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