APPARATUSES, METHODS, AND SYSTEMS FOR DEVICE TRANSLATION LOOKASIDE BUFFER PRE-TRANSLATION INSTRUCTION AND EXTENSIONS TO INPUT/OUTPUT MEMORY MANAGEMENT UNIT PROTOCOLS

Systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. A hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processo...

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Bibliographic Details
Main Authors WANG, Junyuan, XIE, Qianjun, FAN, Zijuan, LI, Weigang, GUO, Kaijie, RAJ, Ashok
Format Patent
LanguageEnglish
French
German
Published 26.06.2024
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. A hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processor core separate from the input/output device and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.
Bibliography:Application Number: EP20210953780