CHIP PACKAGING STRUCTURE AND PREPARATION METHOD FOR CHIP PACKAGING STRUCTURE

• Main Authors: HE, Ran, JIAO, Huifang
• Format: Patent
• Language: English; French; German
• Published: 29.05.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of this application provide a chip package structure and a preparation method. The chip package structure includes a first chip and a first hybrid bonding structure. The first chip is connected to another chip through the first hybrid bonding structure. The first hybrid bonding structure includes a first bonding layer. The first bonding layer is disposed on a side away from a substrate of the first chip, and the first bonding layer includes a first insulation material and a plurality of first metal solder pads embedded in the first insulation material. Each of the plurality of first metal solder pads includes a groove structure. A groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material. The groove structure is filled with a first insulation medium, and a surface of the first insulation medium is flush with the surface of the first insulation material. The chip package structure may improve performance of signal transmission between packaged chips.