IN-MEMORY COMPUTATION SYSTEM WITH COMPACT STORAGE OF SIGNED COMPUTATIONAL WEIGHT DATA

An IMC circuit includes a memory cells arranged in matrix (112). Computational weights for an IMC operation are stored in groups of cells (115AB; 215AB). Each row of groups of cells includes a positive (WL+) and negative (WL-) word line. Each column of groups of cells includes a bit line (BL). The I...

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Bibliographic Details
Main Authors ZAMBOTTI, Paolo Sergio, CARISSIMI, Marcella, ZURLA, Riccardo
Format Patent
LanguageEnglish
French
German
Published 29.05.2024
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An IMC circuit includes a memory cells arranged in matrix (112). Computational weights for an IMC operation are stored in groups of cells (115AB; 215AB). Each row of groups of cells includes a positive (WL+) and negative (WL-) word line. Each column of groups of cells includes a bit line (BL). The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.
Bibliography:Application Number: EP20230212542