MEMORY WRITE METHODS AND CIRCUITS

Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transist...

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Bibliographic Details
Main Authors CHEN, Xiao, HSIEH, Chen-Ju, PAUL, Ayan, CHEN, Po-Hung, JUNG, Chulmin, LI, David
Format Patent
LanguageEnglish
French
German
Published 08.05.2024
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.
Bibliography:Application Number: EP20220744863